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EL4511
Data Sheet June 4, 2003 FN7009.3
PRELIMINARY
Super Sync Separator
The EL4511 sync separator IC is designed for operation in the next generation of DTV, HDTV, and projector applications, as well as broadcast equipment and other applications where video signals need to be processed. The EL4511 accepts sync on green, separate sync, and H/V sync inputs, automatically selecting the relevant format. It is also capable of detecting and decoding tri-level syncs used with the latest HD systems. Unlike standard sync separators, the EL4511 can automatically detect the line rate and locks to it, without the use of an external RSET resistor. The EL4511 is available in a 24-pin QSOP package and operates over the full 0C to 70C temperature range.
Features
* Composite, component, HDTV, and PC signal-compatible * Tri-level & bi-level sync-compatible * Auto sync detection * 150kHz max line rate * Low power * Small package outline * 3.3V and 5V operation
Applications
* HDTV/DTV analog inputs * Video projectors * Computer monitors * Set top boxes
Ordering Information
PART NUMBER EL4511CU EL4511CU-T7 EL4511CU-T13 PACKAGE 24-Pin QSOP 24-Pin QSOP 24-Pin QSOP TAPE & REEL 7" 13" PKG. DWG. # MDP0040 MDP0040 MDP0040
* Security video * Broadcast video equipment
Pinout
EL4511 (24-PIN QSOP) TOP VIEW
XTAL 1 VBLANK 2 SYNCLOCK 3 PDWN 4 SDENB 5 SCL 6 SDA 7 GNDD1 8 HIN 9 SYNCIN 10 VERTIN 11 LEVEL 12 24 XTALN 23 ODD/EVEN 22 VERTOUT 21 HOUT 20 BACKPORCH 19 SYNCOUT 18 VCCD 17 GNDD2 16 GNDA2 15 VCCA2 14 VCCA1 13 GNDA1
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2003. All Rights Reserved. Elantec is a registered trademark of Elantec Semiconductor, Inc. All other trademarks mentioned are the property of their respective owners. Manufactured under U.S. Patent 5,528,303 Manufactured under License, U.S. Patents 5,486,869; 5,754,250
EL4511
Absolute Maximum Ratings (TA = 25C)
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . (VS to GND) +6V Pin Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V, VS +0.3V VCCA1, VCCA2 & VCCD . . . . . . . . . . . . . . . .Must Be Same Voltage Storage Temperature Range . . . . . . . . . . . . . . . . . .-65C to +150C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 125C Ambient Operating Temperature . . . . . . . . . . . . . . . . . 0C to +70C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER GENERAL ISD
VS = VCCA1 = VCCA2 = VCCD = +5V, TA = 25C, NTSC input signal on SYNCIN, no output loads, unless otherwise specified. CONDITIONS MIN TYP MAX UNIT
DESCRIPTION
Digital Supply Current
(Note 1) Standby PDWN = VCCD (Note 2)
15 4 3 2.5 3 3
20 20 20 20 20 20
mA A mA A mA A
ISA2
Rate Acquisition Oscillator Supply Current Analog Processing Supply Current
(Note 1) Standby PDWN = VCCD (Note 1) Standby PDWN = VCCD (Note 2)
ISA1
COMPOSITE SYNC INPUT AT SYNCIN VSYNC VSLICE Sync Signal Amplitude Slicing Level of Sync Signal AC coupled to SYNCIN pin (Notes 1 & 3) After sync lock is attained, see description 140 50 600 mV %
HORIZONTAL AND VERTICAL INPUT AT HIN, VERTIN HSLICE, VSLICE Slice Level of HIN and VERTIN THINL FHINH TVINL FVINH H Sync Width H Sync Frequency V Sync Width V Sync Frequency 3 10.75 2 23 1.4 12.8 150 7 100 V % of H time kHz H lines Hz
LOGIC OUTPUT SIGNALS, HOUT, VOUT, VBLANK, BACKPORCH, ODD/EVEN, SYNCLOCK O/PLOW Logic Low State 1.6mA, VCCD = 5V 1.6mA, VCCD = 3.3V O/PHI Logic High State 1.6mA, VCCD = 5V 1.6mA, VCCD = 3.3V TdHOUT TdSYNCOUT TdBACKPORCH HOUT Timing Relative to Input See timing diagrams 1, 2, 3 & 4 VCCD-0.4 VCCD-0.5 GNDD+0.4 GNDD+0.5 V V
SYNCOUT Timing Relative to Input See timing diagrams 1, 2, 3 & 4 BACKPORCH Timing Relative to Input See timing diagrams 1, 2, 3 & 4
LEVEL OUTPUT DRIVER, LEVEL VLEVEL ZLEVEL 2 X Amplitude of VSYNC O/P Resistance of Driver Stage Refer to description of operation 1.9x 2.15x 450 2.4x
REFERENCE OSCILLATOR FIN FXTAL Reference Input Frequency Crystal Frequency Refer to description of operation Watch crystal (optional) 32.768 50 kHz kHz
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EL4511
Electrical Specifications
PARAMETER VS = VCCA1 = VCCA2 = VCCD = +5V, TA = 25C, NTSC input signal on SYNCIN, no output loads, unless otherwise specified. (Continued) CONDITIONS MIN TYP MAX UNIT
DESCRIPTION
CONTROL INTERFACE SIGNALS PDWN, SDENB, SCL AND SDA VHIGH VLOW O/PVHI O/PVLOW FSCL TCLS TCLH TLC TDC TCD NOTES: 1. NTSC signal; see curves for other rates 2. XTAL pin must be low, otherwise 70A 3. I/P range reduces if VS of 3.3V - 4.5V (see timing diagram 1) Input Logic High Threshold Input Logic Low Threshold SDA O/P Logic High State SDA O/P Logic Low State Serial Control Clock Frequency Setup Time Hold Time Load to Clock Time Hold to Clock Time Clock to Data Out Time @ 1mA @ 1mA 5 30 30 30 30 30 VGNDD+1V VCCD-0.4 GNDD+0.4 V V MHz ns ns ns ns ns VCCD-1V
Pin Descriptions
PIN NUMBER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 PIN NAME XTAL VBLANK SYNCLOCK PWDN SDENB SCL SDA GNDD1 HIN SYNCIN VERTIN LEVEL GNDA1 VCCA1 VCCA2 GNDA2 GNDD2 VCCD1 SYNCOUT BACKPORCH HOUT VERTOUT ODD/EVEN XTALN PIN TYPE Input Logic Output Logic Output Logic Input Logic Input Logic Input Logic BIDIR Power Input Input Input Output Power Power Power Power Power Power Logic Output Logic Output Logic Output Logic Output Logic Output Output PIN DESCRIPTION Crystal input (see Table 5 for details) Vertical blank output Indicates that the EL4511 has locked to the line rate and has found three consecutive "good H lines" Power-down = hi Serial interface enable = low Serial clock Serial data (input for chip setup, output for diagnostic information) Digital ground 1 Horizontal sync Video input, which may incorporate sync signal; connect to Y or G Vertical sync input Indicates 2x amplitude of sync tip vs. back porch; referred to ground Analog ground 1 Analog power supply 1 Analog power supply 2 Analog ground 2 Digital ground 2 Digital power supply 1 Composite sync output Back porch output Horizontal sync output Vertical sync output Odd-Even field indicator output Crystal output (see Table 5 for details)
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EL4511
TABLE 1. SERIAL INTERFACE REGISTER BIT ALLOCATIONS REGISTER REGISTER NUMBER BIT 1 7 6 5:3 2 5 4 1 3 7 6:0 4 7:4 3 2 1 0 6 7:6 7 7:0 8 7:4 3 2 1 0 9 6 5 4 3 2 1 0 13 7:0 14 SIGNAL NAME General Control Reg 1 General Reset AlwaysEnOutputs ModeCtrl General Control Reg 2 Select Fixed Slicing (no S/H) FILTER_ENABLED OE_MODE VBLANK Control Reg 1 EnVBlank VSTPlusBP VBLANK & Polarity Ctrl VFrontPorch DefaultHPolarity DefaultVPolarity EnHPolarityDet EnVPolarityDet Oscillator Control 2 CMuxCtrl <1:0> VBLANK O/P Reg 1 LinesPerFrame <7:0> VBLANK O/P Reg 2 & Misc LinesPerFrame <11:8> En50Slice LPFValid progressive tri-level detect Analog Control Reg 1 ENXTAL ENLEVELBLANKING ENLEVEL ENSYCLAMP ENALOS ENRVIDEO PWRSAVE Absolute Timing Ref 1 CountsPerField <7:0> Absolute Timing Ref 2 & Misc R R Crystal clock periods per field: L.S. Byte. (see description) R/W 0 0 0 0 0 0 0 Set Hi to enable crystal oscillator. Set Hi to enable VLEVEL when not locked. Set Hi to disable VLEVEL output. Set Hi to disable "soft" sync tip clamping in SYNCIN. Set Hi to disable analog loss of signal feature. Set Hi to disable internal biasing on SYNCIN (passive resistor or soft clamp.) Set Hi to put the analog circuit into powersave mode. R R 80h Most significant 4 bits of lines per frame count. Indicates sample and hold front end is being used. Indicates lines per frame has been updated. Not valid for certain types of composite sync. Only valid if tri-level sync detected. R/W R/W R/W R/W TYPE R/W RESET VALUE 00h 0 0 0 10h 0 1 0 90h 1 10h 4Fh 4h 1 1 1 1 22h 0 Multiplexes clock onto VBLANK or Odd/Even. See Table 3. Only valid if VBLANK circuit is enabled Least significant byte of lines per frame count. Number of lines before vertical sync time. HIN polarity on reset if EnHpolarityDet = Lo. VERTIN polarity on reset and if EnVpolarityDet = Lo. Allows EL4511 to detect and set polarity on HIN. Allows EL4511 to detect and set polarity on VERTIN. Enables vertical blank interval detection algorithm. Number of lines after vertical sync time. Necessary for SECAM. May be useful for VCRs. Set Hi to include digital filter on horizontal input. Set Hi for Odd/Even changes on rising edge of vertical. Software reset. Does not affect serial interface. Overrides internal qualification of outputs. Sync acquisition. Selects input signal. See Table 2. DESCRIPTION AND COMMENTS
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EL4511
TABLE 1. SERIAL INTERFACE REGISTER BIT ALLOCATIONS (Continued) REGISTER REGISTER NUMBER BIT 7:6 5 4 3 2 1 0 16 4 3 SIGNAL NAME CountsPerField <9:8> SyncLock CPFValid SetBiLevel VinSyncDet VinPolarity HPolarity Oscillator Settings Observe 2 RateLocked ALOS R Indicates line rate successfully acquired. Analog loss of signal, measured via S/H. H indicates analog signal amplitude is below threshold. TYPE RESET VALUE DESCRIPTION AND COMMENTS Crystal clock periods per field: Bits 9:8. (see description) As sync lock pin. Counts per field valid. Set L if read occurs during an update. Lo: Tri-level mode; Hi: Bi-level mode. Indicates vertical sync on VERTIN successfully acquired. VERTIN polarity setting: Observe. HIN polarity setting: Observe.
VCCA1
VCCD
LEVEL VERTICAL SYNC COMPOSITE SYNC HORIZONTAL SYNC VERTIN SYNCIN HIN SLICING & ANALOG PROCESSING DIGITAL PROCESSING HOUT SYNCOUT VERTOUT VBLANK BACKPORCH POWER DOWN PDWN RESET ODD/EVEN SYNCLOCK LOW ACTIVE SERIAL DATA ENABLE SERIAL CLOCK SERIAL DATA SDENB SCL SDA SERIAL I/F
SYNC LEVEL HORIZONTAL O/P COMP SYNC O/P VERTICAL O/P VERTICAL BLANKING O/P BACK PORCH O/P ODD/EVEN O/P SYNC LOCK O/P
RATE ACQUISITION OSCILLATOR
REFERENCE OSCILLATOR
GNDD1 GNDD2
GNDA1
VCCA2
GNDA2
XTALIN
XTAL
MODE CONTROL PINS
FIGURE 1. BLOCK DIAGRAM
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EL4511
COMPOSITE VIDEO INPUT, FIELD ONE 3H 2 3H 5 3H 8
1 H Sync Interval
3
4 H
6
7
9 .5H
10
19 H
20
21
.H
Start of H Field One Pre-Equalizing Pulse Interval
V Sync Pulse Interval 9 Line Vertical Interval
Post-Equalizing Pulse Interval
SYNC OUT OUTPUT
VOUT OUTPUT tVS
ODD/EVEN OUTPUT
BACKPORCH OUTPUT
HOUT OUTPUT
VBLANK
Notes:
b. The composite sync output reproduces all the video input sync pulses, with a propagation delay. c. Vertical sync leading edge is coincident with the first vertical serration pulse leading edge, with a propagation delay. d. Odd-even output is low for even field, and high for odd field. e. Back porch goes low for a fixed pulse width on the trailing edge of video input sync pulses. Note that for serration pulses during vertical, the back porch starts on the rising edge of the serration pulse (with propagation delay).
FIGURE 2. EXAMPLE OF VERTICAL INTERVAL (525)
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EL4511
COMPOSITE VIDEO INPUT, BEGINNING OF FIELD ONE START OF FIELD ONE 622 623 624 625 1 2 3 4 5 6 7 23 24
SYNCOUT OUTPUT
VOUT OUTPUT
TVS ODD/EVEN OUTPUT
BACKPORCH OUTPUT
HOUT OUTPUT
V BLANK OUTPUT
Notes:
b. The composite sync output reproduces all the video input sync pulses, with a propagation delay. c. Vertical sync leading edge is coincident with the first vertical serration pulse leading edge, with a propagation delay. d. Odd-even output is low for even field, and high for odd field. e. Back porch goes low for a fixed pulse width on the trailing edge of video input sync pulses. Note that for serration pulses during vertical, the back porch starts on the rising edge of the serration pulse (with propagation delay).
FIGURE 3. EXAMPLE OF VERTICAL INTERVAL (625)
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EL4511
SYNCIN 1123 SYNCOUT 1124 1125 1 2 3 4 5 6 7 8 ... 21
HOUT BACKPORCH
VOUT
VBLANK
DEFAULT 20 LINES
ODD/EVEN
ODD FIELD
SYNCIN 560 SYNCOUT 561 562 563 564 565 566 567 568 569 570 ... 583
HOUT BACKPORCH
VOUT VBLANK
DEFAULT 20 LINES
ODD/EVEN EVEN FIELD
FIGURE 4. EXAMPLE OF HDTV 1080I/30 LINE COMPOSITE VIDEO: INTERLACED, ODD & EVEN FIELD
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EL4511
Default 20 Lines
Default 20 Lines
FIGURE 5. HDTV 1080I/25 LINE COMPOSITE VIDEO: INTERLACED ODD & EVEN FIELD (1250 LINES)
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EL4511 Timing Diagram 1 - Example of Horizontal Interval 525/625 Line Composite
CONDITIONS: VCCA1 = VCCA2 = VCCD = +5V, TA = 25C, NO FILTER (REGISTER 2 BIT 4=0)
INPUT DYNAMIC SYNC LEVEL RANGE 0.5V-2V (@VCCA1=5V) SYNC IN 0.5V-1V (@VCCA1=3.3V) 50%
COLOR BURST
WHITE LEVEL VIDEO
VSLICE VSYNC (SYNC TIP VOLTAGE)
VBLANK (BLANKING LEVEL VOLTAGE)
SYNC
SYNC TIP tdSYNCOUT SYNC OUT
DEPENDS ON WIDTH OF INPUT SYNC AT 50% LEVEL
HOUT
tdHOUT
THOUT TBACKPORCH BACKPORCH
tdBACKPORCH
No Filter
PARAMETER tdSYNCOUT tdHOUT tdBACKPORCH THOUT TBACKPORCH NOTE: 1. Delay variation is less than 2.5ns over temperature range DESCRIPTION SYNCOUT Timing Relative to Input HOUT Timing Relative to Input BACKPORCH Timing Relative to Input Horizontal Output Width BACKPORCH (Clamp) Width CONDITIONS See timing diagram 1 See timing diagram 1 See timing diagram 1 See timing diagram 1 See timing diagram 1 TYP (Note 1) 65 470 525 1545 3345 UNIT ns ns ns ns ns
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EL4511 Timing Diagram 2 - Example of Horizontal Interval 525/625 Line Composite
CONDITIONS: VCCA1 = VCCA2 = VCCD = +5V, TA = 25C, FILTER IN (REGISTER 2 BIT 4=1)
COLOR BURST INPUT SYNC LEVEL DYNAMIC RANGE 0.5V-2V (@VCCA1=5V) SYNC IN 0.5V-1V (@VCCA1=3.3V) 50% SYNC TIP tdSYNCOUT SYNC OUT VSYNC (SYNC TIP VOLTAGE)
WHITE LEVEL VIDEO
VSLICE
VBLANK (BLANKING LEVEL VOLTAGE)
SYNC
DEPENDS ON WIDTH OF INPUT SYNC AT 50% LEVEL
HOUT
tdHOUT
THOUT TBACKPORCH BACKPORCH
tdBACKPORCH
Filter In
PARAMETER tdSYNCOUT tdHOUT tdBACKPORCH THOUT TBACKPORCH NOTE: 1. Delay variation is less than 2.5ns over temperature range DESCRIPTION SYNCOUT Timing Relative to Input HOUT Timing Relative to Input BACKPORCH Timing Relative to Input Horizontal Output Width BACKPORCH (Clamp) Width CONDITIONS See timing diagram 2 See timing diagram 2 See timing diagram 2 See timing diagram 2 See timing diagram 2 TYP (Note 1) 220 470 525 1545 3345 UNIT ns ns ns ns ns
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EL4511 Timing Diagram 3 - Example of Horizontal Interval (HDTV) (720p)
CONDITIONS: VCCA1 = VCCA2 = VCCD = +3.3V/+5V, TA = 25C, NO FILTER (REGISTER 2 BIT 4=0)
SYNCIN
tdSYNCOUT SYNC OUT
HOUT
tdHOUT
THOUT TBACKPORCH BACKPORCH
tdBACKPORCH
H Timing for HDTV, No Filter (using 720p input signal)
PARAMETER tdSYNCOUT tdHOUT tdBACKPORCH THOUT TBACKPORCH NOTE: 1. Delay variation is less than 2.5ns over temperature range DESCRIPTION SYNCOUT Timing Relative to Input HOUT Timing Relative to Input BACKPORCH Timing Relative to Input Horizontal Output Width BACKPORCH (Clamp) Width CONDITIONS See timing diagram 3 See timing diagram 3 See timing diagram 3 See timing diagram 3 See timing diagram 3 TYP TYP @ 3.3V @ 5V (Note 1) (Note 1) 56 48 150 275 300 50 36 140 275 300 UNIT ns ns ns ns ns
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EL4511 Timing Diagram 4 - Example of Horizontal Interval (HDTV)
CONDITIONS: VCCA1 = VCCA2 = VCCD = +3.3V/+5V, TA = 25C, FILTER (REGISTER 2 BIT 4=1)
SYNCIN
SYNC OUT
tdSYNCOUT
HOUT
tdHOUT
THOUT TBACKPORCH BACKPORCH
tdBACKPORCH
H Timing for HDTV, With Filter (using 720p input)
PARAMETER tdSYNCOUT tdHOUT tdBACKPORCH THOUT TBACKPORCH NOTE: 1. Delay variation is less than 2.5ns over temperature range DESCRIPTION SYNCOUT Timing Relative to Input HOUT Timing Relative to Input BACKPORCH Timing Relative to Input Horizontal Output Width BACKPORCH (Clamp) Width CONDITIONS See timing diagram 4 See timing diagram 4 See timing diagram 4 See timing diagram 4 See timing diagram 4 TYP TYP @ 3.3V @ 5V (Note 1) (Note 1) 120 112 155 300 300 110 100 140 300 300 UNIT ns ns ns ns ns
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EL4511 Timing Diagram 5 - 720p Standard with Filter in Circuit
This waveform shows the output jitter present on the HOUT signal. The oscilloscope is triggered from the positive reference edge of the composite sync output.
Description of Operation
The EL4511 incorporates the following functional blocks: * Analog I/Ps, processing, and slicing * Signal source and polarity detector * Signal & H rate acquisition block * Advanced sync separator which will detect both conventional and tri-level sync signals * Video lock and level indicators * Reference counter * Computer and control interface
It is possible to force the slicing level to remain at the fixed level of 78mV above the sync tip; Register 2, bit 5 is set High to do this. This can help when dealing with signal that have bursts of noise, or formats that have signals that will modify the sync amplitude measurement process. VGA type of signals will be connected to the HIN and VERTIN pins (use HIN for combined H & V). These are DC coupled signals; they will be sliced at a fixed level of approximately 1.4V. These inputs may be any combination of positive and negative polarities; the EL4511 will invert as required to keep the outputs in the correct polarity. This polarity correction process may be modified with Register 4 bits 3:0.
Analog I/Ps, Processing, and Slicing
The EL4511 has three I/P pins which may be connected to a source of external sync signals. For YPrPb or RGB applications, Y or G should be connected to SYNCIN. For applications with separate horizontal and vertical sync inputs, these should be connected to HIN and VERTIN, respectively. (HIN may also be used for composite sync without video.) Composite video input signals should be connected to SYNCIN. This should be AC coupled from a low impedance source. The input resistance is in the order of 100k. After H lock is obtained, this signal will be "soft clamped" (5k) to approximately 20% of the VCCA1 voltage. In the default mode, the clamping action ensures that the correct slicing levels will be used throughout the field. This operation can be modified through Register 9. The soft clamp can be disabled by setting bit 3 to Hi. Setting bit 1 to high will disconnect the input bias network. Once the acquisition process is complete (see below for description), the slice level will be adaptive. The sync signal is measured from sync tip to blanking level; (Tri-level is measured between negative and positive sync tips). The slice level is then set to 50% of these levels.
Signal and Horizontal Rate Acquisition Block
On power-up, if both HIN and SYNCIN are enabled; the EL4511 will slice the SYNCIN input at 78mV above the negative sync tip level and monitor the sliced signal for up to 320s. If a periodic signal within the specified frequency limits is found to be present, this is assumed to be the horizontal frequency. If no signal is found, the EL4511 will switch to slice and monitor the HIN input at a TTL level. The EL4511 will continue to monitor these two signals in turn until an appropriate signal is detected. If only one of HIN and SYNCIN is enabled, the EL4511 will continuously monitor the selected signal until an appropriate signal is detected; this will give a shorter lock time where only one type of signal is used. At this point, the rate acquisition oscillator lock process (to the H rate signal) will begin.
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EL4511
Advanced Sync Separator
TABLE 2. MODE CONTROL TRUTH TABLE (see also Table 5 for hardware over-ride) Mode Ctrl Reg 1 b5 b4 b3 000 001 010 011 100 101 110 111 1 1 1 1 0 0 0 0 1 1 1 0 1 1 1 1 1 1 1 0 1 0 1 1 0 0 1 1 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 0 0 0 0 1 EnTri Level EnBi Level EnHin TriLevel Hin HinVin Vin Priority Priority Only
Once the line rate has been determined, the signal can be analyzed by the advanced sync separator. This has been designed to be compatible with a wide range of video standards, operating with horizontal line rates up to 150kHz. PAL/NTSC/SECAM; HDTV, including bi-level and tri-level sync Standards and computer display syncs. The EL4511 can be programmed to disable the detection of either bi-level or tri-level sync signals or to prioritize the detection of one sync signal type over the other. If the vertical sync input pin, VERTIN, is enabled, the EL4511 will automatically detect whether a valid signal is present on that pin, and incorporate that signal into the algorithm. Otherwise, the input signal on which the horizontal sync was detected will be treated as a composite sync. The sync separator also includes a qualification scheme which rejects high frequency noise and other video artifacts, such as color burst. The horizontal line rate is automatically acquired from the signal (see above.) A digital filter is included in the signal path to remove noise and glitches; this may be removed if the extra delay it incurs needs to be removed. Setting register 2, bit 4 to Low will remove the filter. After the signal has been identified and the qualification process is complete, the SYNCLOCK pin will go high and the output waveforms will be enabled. These may be enabled all the time by setting register 1, bit 6 to a high state. This can help noisy and varying signals as the revalidation does not have to take place before the signals are available at the outputs, See Figures 2 through 5 for examples of various types of input signal. Part of the signal recognition algorithm uses the number of horizontal lines between vertical pulses. A counter is clocked by the Hclock, this counter is also used to generate vertical timing pulses. This count information is available via the serial I/F; this is a 12 bit number. The lines per frame count is available at register 8, bits 7:4 for the MSBs; the LSBs are available at register 7, bits 7:0. Register 8, bit 2 indicates that the lines/frame counter has been updated when it is high. This counter also generates the VBLANK waveform. Using a look up table, the default blanking is based on number of lines in the field. This operation may be disabled by setting register 3, bit 7 to a low. As this is dependent on application and product usage, this may be modified. Register 3, bits 6:0 will set the number of horizontal lines after VERTOUT leading edge. Register 4, bits 7:4 sets the number of lines before the VERTOUT leading edge.
EnTriLevel, EnBiLevel and EnHinVin; these enable tri-level sync detection, two-level sync detection and separate H/V (VGA) sync detection, respectively. Other signals used to prioritize tri-level syncs (TriLevPriority), separate H/V (Hin Priority), or to only allow signals from HIN/VERTIN (HinVinOnly).
Horizontal Rate Acquisition Oscillator
This oscillator is frequency locked to 512 times the horizontal rate. This clock signal generates the timing and gating signals that are employed internally by the EL4511. This operation is entirely automatic and requires no input from the external circuitry or microprocessor. It is possible to gain access to this oscillator O/P by changing the assignment of pin 2 (VBLANK) or pin 23 (ODD/EVEN). Register 6, bits 7:6 make this selection; see Table 3 for allocations. The oscillator frequency is adjusted at the beginning of the line. At the time of frequency adjustment the clock O/P may have a phase discontinuity.
TABLE 3. ACQUISITION CLOCK MULTIPLEXER CmuxCtrl Reg6 b7 b6 00 01 10 11 Normal Operation Clock multiplexed onto Odd/Even (pin 23) Clock multiplexed onto VBLANK (pin 2) Reserved ACTION
Video Lock and Level Indicators
Loss of video signal can be detected by monitoring the SYNCLOCK pin 3. This pin goes high once the sync separator has detected a valid sync signal and goes low if this signal is lost for more than 20 successive lines. This
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EL4511
signal is also available at register 14 pin 5. Other lock acquisition signals available from the system are listed in Table 4. The sync tip amplitude is buffered with a nominal gain of 2.15 to produce a positive, ground-referenced signal on the LEVEL pin. This output can be used for AGC applications.
TABLE 4. ACQUISITION CONTROL SIGNALS REGISTER 8 8 8 9 9 9 14 16 16 BIT 3 1 0 5 4 2 5 4 3 SIGNAL NAME En50Slice Progressive Tri-Level Detected ENLEVEL BLANKING ENLEVEL ENALOS DESCRIPTION 1=Sample and Hold front end is in use 1=Progressive scan detected 1= Tri-Level syncs detected 1= VLEVEL is available when system is not locked 1=Disable VLEVEL Output 1=Analog loss of signal not used in lock indication. 0 0 0 1 0 1 1 X 1 0 1 X 0 1 1 1 0 1 1 1 1
are no longer valid; (most likely now being an AC signal for the reference clock).
TABLE 5. MODE CONTROL USING PINS 1 & 24 ENXTAL Register9 b6 0 0 0 PIN 1 XTAL PIN 24 XTALN MODE CONTROL Register1 b5 b4 b3 0 0 0 All signals enabled Tri-Level Only Bi-Level Only VGA only Crystal Oscillator is operational DESCRIPTION
Set by Serial I/F
Using the Reference Oscillator and Counter
A counter is provided for measuring the vertical time interval; this counts the clocks at the XTAL pin 1 between vertical pulses. This information is not necessary for the operation of the chip; only for information to the system micro-control. The count value is read from register 14 at bits 7:6 for the MSBs, the LSBs are available in register 13, bits 7:0. Register 14, bit 4 should be a high to indicate that the read operation did not collide with the up-date timing. If the crystal oscillator is enabled through the serial interface (Register 9, bit 6, ENXTAL), the XTAL and XTALN pins will become the crystal input and crystal output pins for the 32.7kHz crystal. It is also possible to drive the XTAL pin with a logic level clock up to a maximum of 50kHz; this signal is only used to measure the vertical rate. Example: Using a 32.768kHz crystal, the count period is 30.52s. With a 20ms vertical rate, there will be approximately 656 cycles (290 Hex) in the "counts per field" registers 13 and 14. With a 16.666'ms vertical rate, the count of 546 (222 Hex) will be seen.
SYNCLOCK Same information as SYNCLOCK pin 3 RateLocked ALOS Line rate is locked Sync Amplitude is below minimum
Mode Decode
In order to allow more flexibility when operating without a serial interface, the XTAL and XTALN pins are decoded by default to enable four control modes. These modes could be used to over-ride sync type used. See Table 5 for details. The all-signal type allowed mode is the same as the default mode when the crystal oscillator is enabled (set bit 6 of Reg9 to 1) except the countsPerField function is disabled in Reg13 and Reg14. The bi-level mode is for bi-level sync only, such as NTSC and PAL. The tri-level mode is for tri-level sync only, such as HDTV signals. The VGA only mode is for computer digital types of signals signal only. The internal pull-up resistors on XTAL & XTALN are very high, these pins should use 10k pull-up/down to operate when not using a crystal. By default, the EL4511 will wake up with Register 9, bit 6 set to Low. This will allow the use of logic levels on pins 1 & 24 to drive register1, bits 5:3 and register 2 bit 0 into the combinations shown in Table 5. To define the mode through the serial interface, the register 9, bit 6 must be set to High, the logic levels on pins 1 & 24
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EL4511
TO SERIAL I/F 8 Q0 Q7 Q6 Q7 REGISTER 13 LD REGISTER 14 LD
VERTOUT TIMING Q0 R CLK 8 Q7 Q8 Q9
10 BIT COUNTER
`1' `0' XTAL (PIN 1) MODE DECODE (SEE TABLE 6) 3 REGISTER 1, BITS 5:3 REGISTER 2, BIT 0
XTALN (PIN 24) REGISTER 9 BIT 6
FIGURE 6. BLOCK DIAGRAM OF REFERENCE OSCILLATOR
Computer & Control Interface
In addition to the mode control pins, the chips default operating mode may be changed by way of a serial interface. This is of the three-wire type, Data, clock and /enable. After the /ENABLE line (pin 5) is taken low, the 16 bits of data on the SDA pin 7 will be clocked into the chip by the clock signal SCL pin 6. See Figure 7. The first bit of the data determines whether it will be a read or write operation. When set to a "0", a write operation will take place. The following 7 bits, select the register to be written to. Finally, the last 8 bits are the data to be written or read. For a read operation, the first bit is a "1".
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EL4511
t(SDENB) IDLE
WRITE TO REGISTER OF EL4511 (WRITE INDICATED WITH ADDRESS = 0XXXXXXX) SDENB t(SCL)HI t(SCL)LO SCL 16 (1/F)*SCL
td(SDENB) SDA td(SCL) START 0 t(SDA) SETUP t(SDA) HOLD LSB
"0"=WRITE
REGISTER ADDRESS 7 BITS
INPUT DATA 8 BITS t(SDENB) IDLE
READ FROM REGISTER OF EL4511 (READ INDICATED WITH ADDRESS = 1XXXXXXX) SDENB t(SCL)HI t(SCL)LO SCL SDA 1 td(SCL) START t(SDA) SETUP t(SDA) HOLD D7 (1/F)*SCL td(SDA)OUT
td(SDENB)STOP 16
D0 td(SDA) OFF
"I"=READ
REGISTER ADDRESS 7 BITS
OUTPUT DATA 8 BITS
FIGURE 7. SERIAL INTERFACE TIMING DIAGRAM
Applications Examples
The following examples show how a system may be configured to operate the EL4511.
4.7F
14
18
15
+ 0.1F
+5V VCCA1 VCCD VCCA2
+5V 0.1F
Application 1 (minimum circuitry application)
In this example, the requirement is for vertical and horizontal timing to be generated from either an NTSC/PAL composite video waveform, or a computer generated image with separate TTL level syncs. The EL4511 has the advantage that the sync separation is carried out over a wide frequency range without the need to adjust "RSET" as required by earlier generations of sync separators. As there is no Microcontroller connected in this example, there is no need for a XTAL at pins 1 & 24. These pins are tied low, this enables the EL4511 to check for either type of input signal (See Table 5 for details.)
TTL HORIZ SYNCS TTL VERT SYNCS
9 75 EL8200 11 75 100nF 10 75 4 1 24 10k
HIN
GNDA2
16
VERTIN
VERTOUT
EL4511
SYNCIN PDWN XTAL GNDD1 GNDA2 XTALN GNDD2 HOUT
22 VERT TIMING TO SYSTEM 21 HORIZ TIMING TO SYSTEM
8
6
13
FIGURE 8. APPLICATIONS DRAWING 1
18
17
7
SDA
SCL
EL4511
Application 2 (application using mode setting logic signals)
In this example, the requirement is to provide the synchronizing information in a small display device. In this example the incoming sync signals may come from one of three sources. Computer, HDTV Set-top Box or an NTSC/PAL tuner. The EL4511 has the advantage that the sync separation is carried out over a wide frequency range without the need to adjust "RSET" as required by earlier generations of sync separators. As there is no Microcontroller connected in this example, there is no need for a XTAL at pins 1 & 24. These pins can be used to force the EL4511 to select the correct operation (and speed up acquisition). Note that a Low Pas Filter is in the NTSC/PAL signal path to reduce noise, glitches and subcarrier. (In signals with bad Croma/Luma gain balance, the subcarrier can extend into the sync slicing level) (See Table 5 for details.)
VIDEO SIGNALS (RGB) H SYNC V SYNC 75 VIDEO SIGNALS (HDTV) HDTV EL8400 COMPONENT SYNCS 75 620 510pF CVBS 75 14 18 15 + 4.7F 0.1F VCC VCCA1 VCCA2 VCCD VCC 0.1F COMPOSITE 75
VIDEO SIGNAL (CVBS)
9
HIN
GNDA2
16
11 COMPUTER HDTV NTSC/PAL VCC 10k
VERTIN
VERTOUT
22
VERTICAL TIMING
100nF
EL4511
10 4 1 SYNCIN PDWN XTAL GNDD1 GNDA2 GNDD2 HOUT 21 HORIZONTAL TIMING
8
6
13
FIGURE 9. APPLICATIONS DRAWING 2
19
17
7
SDA
10k
SCL
24
XTALN
EL4511
Application 3 (application using a microcontroller interface)
In this example, the requirement is to provide the synchronizing information in a video digitizing interface. This example is very similar to the example in application 2. In this example the incoming sync signals may come from one of three sources. Computer, HDTV source or an NTSC/PAL device. As there is a Microcontroller connected in this example, a 32.768kHz XTAL is connected to pins 1 & 24; this will allow the system microcontroller to gather timing information for the vertical rate. To enable the crystal oscillator, register 9, bit 6 must be set to a high. Note that a Low Pass Filter is in the NTSC/PAL signal path to reduce noise, glitches and subcarrier. (In signals with bad Croma/Luma gain balance, the subcarrier can extend into the sync slicing level). As some of the signals in this application were non standard formats, the fixed slice mode is used by setting register 2, bit 5 to a high. Register 1, bit 6 is also set to a high. This forced the EL4511 to provide outputs even when the input signals are not recognized by the internal algorithms.
VIDEO SIGNALS (RGB) H SYNC V SYNC 75 VIDEO SIGNALS (HDTV) HDTV EL8400 COMPONENT SYNCS 75 620 510pF CVBS 75 14 18 15 + 4.7F 0.1F VCC VCCA1 VCCD VCCA2 VCC 0.1F COMPOSITE 75
VIDEO SIGNAL (CVBS)
9
HIN
GNDA2
16
11
VERTIN
VERTOUT
22
VERTICAL TIMING HORIZONTAL TIMING VIDEO CLAMP PLL COAST
100nF
EL4511
10 4 1 SYNCIN PDWN XTAL
HOUT
21
BACKPORCH
20
GNDD1
GNDA2
8
5
6
13
17
7
SDA
SCL
24
XTALN
GNDD2
SDENB
32.768kHz CRYSTAL
VBLANK
2
TO MICROCONTROLLER
FIGURE 10. APPLICATIONS DRAWING 3
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 20

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